This invention relates to a method of producing a semiconductor device, particularly, to a method of electrically insulating a prescribed element region formed in a semiconductor substrate from other element regions.
Recently, memory cells of a semiconductor memory device tend to be very finely formed on a semiconductor substrate in order to increase the density of integration. The surface area of a semiconductor substrate is divided into a plurality of element regions by field insulation layers, and memory cells are formed in the element regions thus divided. Of course, the memory cells are electrically insulated from each other by the field insulation layer.
An erasable and programmable read only memory (EPROM) comprises a p-channel floating gate MOS transistor acting as a memory cell as shown in, for example, FIG. 1. In the prior art shown in FIG. 1, a field insulation layer 10 is formed on an n-type semiconductor substrate 12. It is seen that an n.sup.+ -type region 14 is formed in the substrate 12 right under the field insulation layer 10. P.sup.+ -type regions 16A, 16B acting as source and drain regions are formed in contact with the p.sup.+ -type region 14 within an element region surrounded by the field insulation layer 10. The element region is covered with an insulation layer 18. It is seen that a floating gate electrode 20 is formed on the channel region positioned between the p.sup.+ -type regions 16A and 16B with the insulation layer 18 interposed between the electrode 20 and the channel region. Also, a control gate 22 is formed on the floating gate electrode 20 with an insulation layer interposed therebetween. Further, an insulation layer 24 is formed to cover the control gate electrode 22, floating gate electrode 20 and field insulation layer 10. Still further, source and drain electrodes 26A, 26B are formed in ohmic contact with the p.sup.+ -type regions 16A, 16B via contact holes made through the insulation layers 24 and 18 superposed one upon the other.
The n.sup.+ -type region 14 shown in FIG. 1 is intended to prevent the conductivity type of the substrate 12 from being inverted into a p-type in the region directly under the field insulation layer 10 by the stationary charge of the field insulation layer 10 and the electric field produced by the wiring (not shown) formed on the insulation layer 24. If the inversion occurs, a short-circuit current flows between the p.sup.+ -type regions 16A, 16B and the other element regions.
Where the floating gate MOS transistor is used as a memory cell, such a large potential difference as -20 V or more with respect to the source electrode and substrate is applied to the gate electrode and drain electrode during the programming operation in order to generate hot holes between the p.sup.+ -regions 16A and 16B for charging the floating gate electrode 20. The voltage applied to the p.sup.+ -type region 16B can be maintained within a range which does not exceed the breakdown voltage in the reverse direction of the pn junction formed between the p.sup.+ -region 16B and the n.sup.+ -region 14. In the MOS transistor shown in FIG. 1, the breakdown voltage in the reverse direction of the pn junction mentioned above greatly depends on the impurity concentration of the n.sup.+ -type region 14, because the impurity concentration of the p.sup.+ -type region 16B is set at 10.sup.20 cm.sup.-3 or more in order to reduce the wiring resistance and because the impurity concentration of the n.sup.+ -type region 14 is higher than that of the substrate 12. Since a voltage of 20 V is applied to the pn junction formed between the p.sup.+ -type region 16B and the n.sup.+ -type region 14, the upper limit of the impurity concentration of the n.sup.+ -type region 14 may be about 5.times.10.sup.16 cm.sup.3.
On the other hand, the field insulation layer 10 tends to be thin in accordance with miniaturization of the memory cell. As a result, the conductivity type of the n.sup.+ -type region 14 right under the field insulation layer 10 is more likely to be inverted. The inversion of the conductivity type can be prevented by increasing the impurity concentration of the n.sup.+ -type region 14. However, the increase in the impurity concentration results in a lowered breakdown voltage in the reverse direction of the pn junction between the n.sup.+ -type region 14 and the p.sup.+ -type region 16B. If the impurity concentration of the n.sup.+ -type region 14 exceeds the upper limit mentioned above, it is impossible to apply a voltage of 20 V to the p.sup.+ -type region 16B. It follows that the construction of the memory cell (or floating gate MOS transistor) shown in FIG. 1 is unsuitable for increasing the degree of integration of the memory device.
A memory cell as shown in FIG. 2 is also known to the art. The cell shown in FIG. 2 is equal to that shown in FIG. 1 except that, in FIG. 2, a p.sup.- -type region 28 is formed in contact with both the n.sup.+ -type region 14 and the p.sup.+ -type region 16B within the element region surrounded by the field insulation layer 10. In the prior art of FIG. 2, the pn junction formed between the p.sup.- -type region 28 and the n.sup.+ -type region 14 exhibits a relatively high breakdown voltage in the reverse direction because the p.sup.- -type region 28 has a low impurity concentration, compared with the p.sup.+ -type region 16B.
However, the conventional method of producing the memory cell shown in FIG. 2 makes it necessary to employ an impurity diffusion step (or ion implantation step) twice for forming the p.sup.+ -type region 16B and the p.sup.- -type region 28. In addition, the material used as a mask pattern in the impurity diffusion step must be subjected to a patterning treatment. What should be noted is that it is necessary to take a masking error into consideration. Particularly, the p.sup.- -type region 28 is positioned outside the p.sup.+ -type region 16B in the memory cell of FIG. 2, with the result that the cell shown in FIG. 2 requires an element region larger than that in FIG. 1.
A memory cell shown in FIG. 3 is also known to the art. The cell shown in FIG. 3 is equal to that shown in FIG. 1 except that, in FIG. 3, an n-type region 29 is formed directly under the field insulation layer 10 in contact with both the p.sup.+ -type region 16B and the n.sup.+ -type region 14. In FIG. 3, the element region need not be larger than in FIG. 1. However, an impurity diffusion step must be carried out twice in the construction of FIG. 3 for forming the n.sup.- -type region 29 and the n.sup.+ -type region 14.